The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same.
Demands for digital cameras have increased tremendously together with the development of the image communication using the internet. Furthermore, demands for miniature camera modules have increased according to the increasing supply of mobile communication terminals attached with cameras such as personal digital assistant (PDA), international mobile telecommunications-2000 (IMT-2000), and code division multiple access (CDMA).
An image sensor module using the basic composing element such as a charge coupled device (CCD) or a CMOS image sensor have been widely used for a camera module. An image sensor includes color filters to embody color images. The color filters are aligned over a photo sensing unit which receives light from outside, and generates and stores photocharges. Such color filter array (CFA) includes three colors of red (R), green (G), and blue (B), or yellow, magenta, and cyan. Generally, the three colors of red, green, and blue are used in a color filter array of a CMOS image sensor.
The image sensor is a semiconductor device which converts optical images into electrical signals. As described earlier, the CCD and CMOS image sensors are developed and widely used. The CCD includes metal-oxide semiconductor (MOS) capacitors disposed close to each other, wherein charge carriers are stored and transferred in the capacitors. On the contrary, the CMOS image sensor employs a switching method which uses a CMOS technology to form MOS transistors for the same number as the pixels, and successively detects outputs using the MOS transistors. The CMOS technology uses a control circuit and a signal processing circuit as peripheral circuits.
However, the CCD may have a number of limitations including the complicated driving method, the large power consumption, the complicated processes generally requiring many masking processes, and the difficulty to embody the signal processing circuit in the CCD chip, having complications to form one chip. Thus, researches on developing CMOS image sensors using sub-micron CMOS fabrication technology have been actively conducted to overcome such difficulties of the CCD.
The CMOS image sensor embodies images by forming a MOS transistor and a photodiode in a unit pixel, and successively detecting signals using the switching method. Using the CMOS fabrication technology may decrease power consumption, may allow performing simpler processes using approximately 20 masks compared to the CCD process using approximately 30 to 40 masks, and may allow forming one chip with various signal processing circuits.
Generally, the CMOS image sensor includes a photo sensing unit for sensing light and a logic circuit unit for processing the light sensed through the photo sensing unit into an electrical signal to convert into data. Attempts have been made to increase a ratio of a surface area of the photo sensing unit with respect to the total area of the image sensor device to increase photo sensitivity. Hereinafter, such ratio is referred to as a fill factor. However, it may be difficult to increase the fill factor within a limited surface area because the logic circuit unit may not be fundamentally removed.
FIG. 1 illustrates a circuit diagram showing a unit pixel of a typical CMOS image sensor. The unit pixel includes one photodiode and four N-channel MOS (NMOS) transistors. In more detail, the unit pixel includes: the photodiode for receiving incident light and generating photocharges; a transfer transistor Tx for transferring the accumulated photocharges from the photodiode to a floating diffusion region FD; a reset transistor Rx for setting an electric potential of the floating diffusion region FD to a desired value and discharging the photocharges to reset the floating diffusion region FD; a drive transistor Dx for receiving a voltage of the floating diffusion region FD through a gate and thus functioning as a source follower buffer amplifier; and a select transistor Sx for performing an addressing role by switching.
FIG. 2 illustrates a simplified layout of the unit pixel of the typical CMOS image sensor shown in FIG. 1. FIG. 3 illustrates a cross-sectional view of the unit pixel shown in FIG. 2 in a direction along a perforated line I-I′.
Referring to FIGS. 2 and 3, a method for fabricating a typical CMOS image sensor is described as follows. A P− epitaxial layer 12 lowly doped with P-type impurities is grown over a P+ substrate 11 highly doped with P-type impurities. A shallow trench isolation (STI) process is performed on certain portions of the P− epitaxial layer 12 to form isolation structures 13 for isolating unit pixels. A subsequent thermal treatment process is performed to form a P− well 14 in a certain portion of the P− epitaxial layer 12 through lateral diffusion in a manner that the P− well 14 includes the drive transistor Dx and the select transistor Sx.
A third gate electrode 17C of the drive transistor Dx and a fourth gate electrode 17D of the select transistor Sx are formed over the P− well 14, and a first gate electrode 17A of the transfer transistor Tx and a second gate electrode 17B of the reset transistor Rx are formed over the P− epitaxial layer 12. At this time, each of the first to fourth gate electrodes 17A, 17B, 17C, and 17D of the four transistors includes a gate oxide layer 15 and a polysilicon layer 16.
A low concentration ion implantation process using N-type impurities is performed on a portion of the P− epitaxial layer 12 exposed on one side of the first gate electrode 17A of the transfer transistor Tx, i.e., a photodiode region, to form an N− diffusion layer 18.
A low concentration ion implantation process using N-type impurities is performed on portions of the substrate structure exposed on both sides of the third gate electrode 17C of the drive transistor Dx and the fourth gate electrode 17D of the select transistor Sx to form lightly doped drain (LDD) regions 19, which are lowly doped ion implantation regions. Although not illustrated, such LDD regions may be formed in other portions of the substrate structure exposed on both sides of the first and second gate electrodes 17A and 17B of the transfer transistor Tx and the reset transistor Rx, respectively.
A low concentration ion implantation process using P-type impurities is performed with an ion implantation tilt angle to form halo regions 20 between the LDD regions 19. The halo regions 20 are lowly doped ion implantation regions. The LDD regions 19 and the halo regions 20 are formed to reduce a short channel effect of the transistors.
An insulation layer for use as spacers is formed over the resultant substrate structure in a manner to cover the first to fourth gate electrodes 17A, 17B, 17C, and 17D of the transistors. A blanket etch process such as an etch-back process is then performed to form spacers 21 on both sidewalls of the first to fourth gate electrodes 17A, 17B, 17C, and 17D.
P-type impurities are ion implanted with a low ion implantation energy into a portion of the substrate structure exposed on one side of the transfer transistor Tx to form a P0 diffusion layer 22 in the N− diffusion layer 18. Thus, a shallow PN junction including the P0 diffusion layer 22 and the N− diffusion layer 18 is formed, and a PNP type photodiode including the P− epitaxial layer 12, the P0 diffusion layer 22 and the N− diffusion layer 18 is formed.
A high concentration ion implantation process using N-type impurities is performed on portions of the substrate structure exposed on both sides of the first to fourth gate electrodes 17A, 17B, 17C, and 17D of the transistors to form a first to a fourth highly doped ion implantation regions 23A, 23B, 23C, and 23D. The first highly doped ion implantation region 23A will function as a floating diffusion region FD. Processes for forming metal lines, color filters, and micro lenses are then performed to form the image sensor.
FIG. 4 illustrates an enlarged cross-sectional view of a region ‘A’ of the typical CMOS image sensor shown in FIG. 3. Referring to FIGS. 3 and 4, the first highly doped ion implantation region 23A formed between the first gate electrode 17A of the transfer transistor Tx and the second gate electrode 17B of the reset transistor Rx is used as a floating diffusion region FD. The second highly doped ion implantation region 23B formed between the second gate electrode 17B of the reset transistor Rx and the third gate electrode 17C of the drive transistor Dx is used as an ohmic contact layer to be coupled to a power supply voltage VDD. The fourth highly doped ion implantation region 23D formed between the fourth gate electrode 17D of the select transistor Sx and the isolation structure 13 is used as an ohmic contact layer to be coupled to an output terminal Vout. The first, second, and fourth highly doped ion implantation regions 23A, 23B, and 23D are generally required to be formed for the aforementioned functions. However, the third highly doped ion implantation region 23C formed between the third gate electrode 17C of the drive transistor Dx and the fourth gate electrode 17D of the select transistor Sx is not used as an ohmic contact layer, unlike the second and fourth highly doped ion implantation regions 23B and 23D. Thus, it is not generally required to form the third highly doped ion implantation region 23C using the high concentration ion implantation process.
As mentioned above, the CMOS image sensor may have an advantage of simplifying processes when compared to the CCD because the CMOS image sensor is formed using the CMOS fabrication technology. Furthermore, high-density pixels may be embodied by minimizing the size of the unit pixels within the permissible range of the semiconductor fabrication devices used in the CMOS fabrication technology.
However, pixels with even higher density are generally required in order to maintain the competitiveness of the CMOS image sensor. The size of the pixels is often needed to be reduced to embody such high-density pixels. However, when the pixel size is reduced, the size of the photodiode may become smaller relative to the pixel size, reducing the fill factor. Eventually, device characteristics may be deteriorated.